Conventional variable gain amplifiers are disclosed in U.S. Pat. No. 5,757,230 (5,757,230) published May 23, 1998 and U.S. Pat. No. 5,886,579 (5,886,579) published Mar. 23, 1999.
In general, a variable gain amplifier is abbreviated as a VGA. Up to now, approximation methods of implementing the exponential characteristic have been well-known, including an approximation method using Taylor's expansion.                               e          x                ≈                  1          +          x          +                                    1              2                        ⁢                          x              2                                                          (        1        )            
and an approximation method using the bilinear transformation                               e          x                ≈                                            1              +              x                                      1              -              x                                .                                    (        2        )            
Referring now to FIG. 16, a graph illustrating the relationship between the true exponential characteristic (exp(x)) and the expressions of expressions (1) and (2) is set forth.
As seen from FIG. 16, the slope for expression (2) is inconsistent and thus not a correct approximation of exp(x). A better expression is                               e                      2            ⁢            x                          ≈                                            1              +              x                                      1              -              x                                .                                    (        3        )            
In the conventional VGA described in U.S. Pat. Nos. 5,757,230 and 5,886,579, the exponential characteristic is approximated using the bilinear transformation as shown in expression (2) and better approximated in expression (3). The conventional variable gain amplifier show in the above-mentioned publications will now be described.
Referring now to FIG. 17, a circuit schematic diagram of a conventional variable gain amplifier (VGA) is set forth and given the general reference character 1700. Conventional VGA 1700 is described in the above-mentioned U.S. Pat. Nos. 5,757,230 and 5,886,579.
In conventional VGA 1700, a gain controller 1710 receives a gain control signal X as a voltage and provides a control signal C1 as a voltage input to an operational transconductance amplifier (OTA) 1720. Because gain control signal X is a voltage input and control signal C1 is a voltage input, OTA 1720 is a multiplier having a voltage input. OTA 1720 as a multiplier is shown in FIG. 18 (FIG. 2 of U.S. Pat. No. 5,757,230).
Referring to FIG. 18, a circuit schematic diagram of a conventional multiplier is set forth and given the general reference character 1800. Conventional multiplier 1800 is used as OTA 1720 in conventional VGA 1700.
Conventional multiplier 1800 includes MOS (metal-oxide-semiconductor) transistors (M1A, M1B, M2A, and M2B). Drain currents (ID1A, ID2A, ID1B, and ID2B) of MOS transistors (M1A, M1B, M2A, and M2B), respectively, comprising conventional multiplier 1800 are represented such that:                               I          D1A                =                              β            ⁡                          (                                                V                  CM                                +                                                      V                    IN                                    2                                -                                  V                  S                                -                                  V                  TH                                            )                                2                                    (        4        )                                          I          D1B                =                              β            ⁡                          (                                                V                  CM                                +                                                      V                    IN                                    2                                -                                  V                  B                                -                                  V                  S                                -                                  V                  TH                                            )                                2                                    (        5        )                                          I          D2A                =                              β            ⁡                          (                                                V                  CM                                +                                                      V                    IN                                    2                                -                                  V                  S                                -                                  V                  TH                                            )                                2                                    (        6        )                                          I          D2B                =                              β            ⁡                          (                                                V                  CM                                +                                                      V                    IN                                    2                                -                                  V                  B                                -                                  V                  S                                -                                  V                  TH                                            )                                2                                    (        7        )            
Herein, β is a transconductance parameter of MOS transistors (M1A, M1B, M2A, and M2B) and represented as β=μ(COX/2)(W/L), where μ is the effective mobility of carriers, COX is the gate oxide film capacitance per unit area, W is the gate width, and L is the gate length of the respective MOS transistors (M1A, M1B, M2A, and M2B). Also, in expressions (4) to (7), VIN is the input voltage, VCM is the input common mode voltage, VTH is the threshold voltage, and VS is the common source voltage. In FIG. 18, the gate voltages of MOS transistors (M1A, M1B, M2A, and M2B) are VCM+VIN/2, VCM+VIN/2−VB, VCM+VIN/2, and VCM+VIN/2−VB, respectively. Supposing that the gate-source voltage is VGS, the above expressions (4) to (7) are derived from the drain current ID=(VGS−VTH)2.
When the sources of MOS transistors (M1A, M1B, M2A, and M2B) are commonly connected and driven by a current I0, the conditional expression resultsID1A+ID1B+ID2A+ID2B=I0  (8)
When the source is grounded, the conditional expression (8) is unnecessary.
Solving expression (8) using expressions (4) to (7),                                           I            D1B                    +                      I            D2A                          =                                            I              0                        2                    -                      β            ⁢                                                   ⁢                          V              IN                        ⁢                          V              B                        ⁢                                                   ⁢                          (                                                                    V                    IN                    2                                    +                                      V                    B                    2                                    +                                                                                                        V                        IN                                            ⁢                                              V                        B                                                                                                                ≤                                                      I                    0                                                        2                    ⁢                                                                                   ⁢                    β                                                              )                                                          (        9        )                                                      I            D1A                    +                      I            D2B                          =                                            I              0                        2                    -                      β            ⁢                                                   ⁢                          V              IN                        ⁢                          V              B                        ⁢                                                   ⁢                          (                                                                    V                    IN                    2                                    +                                      V                    B                    2                                    +                                                                                                        V                        IN                                            ⁢                                              V                        B                                                                                                                ≤                                                      I                    0                                                        2                    ⁢                                                                                   ⁢                    β                                                              )                                                          (        10        )            can be obtained. Expressions (9) and (10) represent the current characteristics within the linear operation range of MOS transistors (M1A, M1B, M2A, and M2B).
FIG. 19 is a graph illustrating the linear operation obtained. When the source is grounded, conditions as indicated within the parentheses in expressions (9) and (10) are unnecessary.
From the above, a circuit analysis for a conventional multiplier 1800 employed in the conventional VGA 1700 as described in the above-mentioned U.S. Patents is made. FIG. 20 is a circuit schematic diagram showing the conventional VGA using a multiplier as the OTA (see FIG. 3 of U.S. Pat. No. 5,757,230).
In a second OTA 2020 shown in FIG. 20, the sources of four MOS transistors (M3A, M3B, M4A, and M4B) are grounded. However, because a constant current source 10 is connected between the power supply VDD and the drains, the second OTA 2020 has the sum of current flowing through the four MOS transistors (M3A, M3B, M4A, and M4B) which is equal to a constant value I0.
Accordingly, the conditions indicated within parentheses ( ) in expressions (9) and (10) are applied to the second OTA 2020 consisting of four MOS transistors (M3A, M3B, M4A, and M4B) having grounded sources.
Also, a control voltage VBF is applied to the conventional multiplier comprising a first OTA 2010 and a control voltage VBB is applied to the conventional multiplier comprising the second OTA 2020. If the control voltagesVBF∝1+x  (11)VBB∝1−x  (12)
are applied, the voltage gain of the VGA is represented as                               G          v                =                              1            +            x                                1            -            x                                              (        13        )            
and the bilinear transformation as indicated in expression (2) can be realized. When represented in dB (decibel), the bilinear transformation as indicated in expression (2) can be approximated by the exponential characteristic (e2x) with a slope of double ex.
As described above, in a conventional VGA with the gain changed exponential by a control signal in this manner, by using an OTA as a multiplier of an inputted voltage, when the control voltage is increased, the available input voltage range is narrowed by a corresponding amount. Therefore, in that above-mentioned conventional VGA, it is required to provide a wide input voltage range for the multiplier by setting the tail current to a large value in order to keep the variable width of voltage gain in the VGA. Thus, it is difficult to decrease the driving current.
In view of the above discussion, it would be desirable to provide a variable gain amplifier (VGA) circuit that may have a gain changed exponentially in response to a control signal and may be operable at a low voltage with a small circuit current. It would also be desirable to provide a VGA circuit that may have reduced variations due to temperature. It would also be desirable to provide a VGA circuit that may have a simple circuit configuration and may consume less chip area.